1. Field of the Invention
This invention relates to methods of fabricating a packaging structure, and more particularly, to a method of fabricating a packaging structure that may increase the yield and reduce the whole cost.
2. Description of Related Art
According to the modern wire-bonding semiconductor packaging technology, an inactive surface of a semiconductor chip is mounted on a packaging substrate, a plurality of electrode pads are installed on an active surface of the semiconductor chip. A plurality of wire-bonding pads are installed on a surface of the packaging substrate on which the semiconductor chip is mounted, and are electrically connected via bonding wires to the electrode pads, allowing the semiconductor chip to be electrically connected to the packaging substrate.
A packaging substrate of the prior art comprises a core board and two built-up structures that are symmetrically installed on two opposite surfaces of the core board. The use of the core board results in the increasing of wire length and structure thickness, which is contradictory to the compact demand of modern electronic products. Accordingly, a packaging substrate having a coreless structure comes to the market, which has a shorter wire length and thinner structure and meets the compact demand.
A method of fabricating a wire-bonding packaging substrate according to the prior art includes: providing a complete panel of substrate body that has a front-end fabricating process completed, an outermost circuit of the complete panel of substrate body having a plurality of wire-bonding pads and an insulating protection layer; forming a plurality of openings in the insulating protection layer, allowing the wire-bonding pads of the built-up structure to be exposed from the openings; forming a surface treatment layer on the exposed wire-bonding pads, so as to form a complete panel of packaging substrates; cutting the complete panel of packaging substrates into a plurality of packaging substrate units or a plurality of packaging substrate strips, each of the packaging substrate strips having a plurality of packaging substrate units; and, transferring the packaging substrate strips to a packaging factory for subsequent chip attachment, packaging and/or singulation processes.
However, if the chip attachment and packaging processes are performed after the complete panel of packaging substrates is cut into the packaging substrate units, only one of the packaging substrate units is processed at one time, which reduces the yield and increases the cost. Moreover, if the chip attachment, packaging and singulation processes are performed after the complete panel of packaging substrates is cut into the packaging substrate strips, each of the packaging substrate strips has to have a frame reserved for the packaging substrate strip to assist during the manufacturing processes. The frame occupies too much the area and wastes the material cost.
With the packaging substrate becoming thinner and thinner, it is more and more difficult to perform the chip attachment or packaging process on the packaging substrate units or packaging substrate strips.
If the chip attachment, packaging and singulation processed are performed on the complete panel of substrate, without cutting the complete panel of packaging substrates into a plurality of packaging substrate units or a plurality of packaging substrate strips in advance, a larger semiconductor equipment is required. Accordingly, the equipment cost is increased. Besides, the larger the area of the complete panel of packaging substrates is, the lower the precision becomes. Therefore, the final packaging structure units have a larger fabricating error, which affects the yield.
Therefore, how to solve the problems of the method of fabricating a packaging structure of the prior art that the fabricating steps are complicated, yield is low, too many effective area of the substrate is wasted and the cost is high is becoming one of the most popular issues in the art.